Semiconductor memory devices are continually being designed to be made smaller, faster, and to require less power such that they may be incorporated in portable devices that run on battery power. SRAM is volatile memory widely used in laptop computers and personal digital assistants (PDAs) in which each memory cell includes a transistor-based bi-stable latch that is either in an ‘on’ state or an ‘off’ state. SRAM devices may include a matrix of thousands of individual memory cells fabricated on an integrated circuit (IC) chip.
Conventional SRAM arrays have high power consumption due to current leakage when the SRAM array is in a normal operation condition in which data is not being read from or written to the SRAM array. To reduce the leakage current and power consumption of SRAM arrays, a self biased diode is often coupled between low voltage supply VSS and the SRAM array. However, self-biasing diodes experience significant variations across process, voltage, and temperature (“PVT”), which causes problems with data retention and leakage optimization.
For example, when self-biasing diode is in an off state in which current does not flow through the diode, charge accumulates at the node between the diode and the SRAM array thereby increasing the voltage at the node, which reduces the voltage drop across the SRAM array, i.e., the retention voltage. The reduction in the retention voltage is exacerbated by variations in the threshold voltage of the self-biasing diode across PVT variations.
Accordingly, an improved SRAM design is desirable.